2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process

نویسندگان

  • Chun-Yu Lin
  • Ming-Dou Ker
چکیده

With the consideration of low standby leakage in nanoscale CMOS processes, a new 2×VDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCRbased) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only ~200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.

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تاریخ انتشار 2010