2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process
نویسندگان
چکیده
With the consideration of low standby leakage in nanoscale CMOS processes, a new 2×VDD-tolerant ESD clamp circuit was presented in this paper. The new ESD clamp circuit had a high-voltage-tolerant ESD detection circuit to improve the turn-on efficiency of the silicon-controlled-rectifier-based (SCRbased) ESD device. This design had been successfully verified in a 65-nm CMOS process. The leakage current of this ESD clamp circuit under normal circuit operating condition was only ~200 nA. Besides, this ESD clamp circuit can achieve 4.8-kV HBM ESD robustness. Therefore, this design was very suitable for mixed-voltage I/O interfaces in nanoscale CMOS processes.
منابع مشابه
Design of 2×VDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology
A low-leakage 2×VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit composed of the siliconcontrolled rectifier (SCR) device and new ESD detection circuit, realized with only thin-oxide 1× VDD devices, has been proposed with consideration of gate leakage current. By reducing the voltage across the gate oxides of the devices in the ESD detection circuit, the whole power-rail ESD ...
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